Figure 26 - The final version of the dual buffer VGA generator schematic
Figure 26 - The final version of the dual buffer VGA generator schematic

The Schematic shows how the SRAM feeds the video DAC, controlled by the addresses and control lines sent from the AVR. The new schematic is certainly more complex, but the functionality of the system is basically the same as before except that during the horizontal active pixel time, only addresses are sent, not pixels. The addresses tell the SRAM which pixels are to be sent during the active pixel time, and the "page select" pin on PORT B.5 allows the switching of video buffers so that the main loop can draw on a one buffer as the video driver sends out the other to the VGE monitor. When the main loop has completed drawing to the hidden buffer, a simple routine swaps the two banks on the next vertical banking period and the new frame is displayed on the monitor. This way, flicker free animations and drawing can be done.

Since the data from the SRAM has to first move through the 74HC245, the AVR has the ability to shut off all data to the DAC by simply dropping the OE pin on the 254 low. Since the AVR data port must also share the data bus with the SRAM, the video rendering system must disable the AVR data port (PORT D) right before accessing the SRAM to avoid a bus collision. This is done automatically so that the main loop does not have to waste time or worry about video timing. Other than the addition of the two ICs, most of the hardware and software remain the same, keeping to the same basic timings and routines.

Figure 27 - The final version completed on a solderless breadboard
Figure 27 - The final version completed on a solderless breadboard

There is one unused pin on PORT B.6 called "joystick", and I planned to run this IO pin to another 74HC245 to allow reading of a joystick into the data port but ran out of time to complete this part. I only gave myself a weekend to do this project, so if you want to add a joystick or keyboard to the circuit, just use the free IO line to toggle another buffer to allow reading or writing another 8 bit device. The new source code has quite a bit of improvement and some routines to draw text and graphics, so I will go through the changes and then preset an empty VGA driver framework that can be used to create your own games or demos.

< Here is the dual buffer demo source code in AVR assembly >

Let's start by examining the changes made to the video rendering interrupt routine under "HORIZONTAL ACTIVE LINE = 512 CYCLES - 32 / 2 = 240 PIXELS". The system is capable of drawing 256 horizontal pixels, but I simply ran out of clock cycles needed to control all of the new features such as blanking, sound, and the dual bank switching, so I "stole" some time from the horizontal active time by giving up 16 pixels (32 clock cycles). So the final resolution is a perfect square of 240 pixels by 240 pixels, which makes it easy to calculate graphics. Most monitors will either stretch the line or display a small black border on each side of the screen due to the lost 16 pixels.

The active video line starts by first swapping the video buffers by toggling PORT B.5 then it resets the horizontal address counter to zero just before turning on the HC74245 DAC switch by dropping PORT B.2 low. The next 480 cycles are nothing more than address increments, sending the value of the horizontal address counter to the low address bus on PORT A feeding the SRAM. Since the high address bus has already been set on PORT C, the proceeding 480 cycles send out 240 address, hence delivering 240 pixels to the VGA monitor through the 74HC245 and then through the resistor DAC. At the end of this long string of INCs and OUTs, the blanking period begins by setting PORTB.2 high to shut off all data feeding the DAC. The value on PORT B.5 is once again swapped, returning the buffers back to the state before the pixels were drawn. So, basically the new horizontal active line time is spent turning on the DAC and sending 240 address to the SRAM while it is in the output enable state.

Now, let's look back to the beginning of the video rendering interrupt where it begins by controlling the horizontal and vertical sync pulses. There are only 76 cycles available, but in this time the code manages to equalize the interrupt latency quirkiness, save all the main loop registers to the stack, set the SRAM addresses, toggle the sync pins, and control an important register (R25) called "MemReady", which allows the main loop to know when it is safe to have control of the SRAM for reading or writing. Without this MemReady flag, the main loop and video driver may try to access the same address and cause a flicker on the screen. By checking the status of R25 just before a read or write, this collision is avoided, making all animations and graphics routines flicker free.

Now onto "HORIZONTAL BACK PORCH = 36 CYCLES", where in only 36 cycles, a simple sound system has been added along with the restoring of main loop registers from the stack and the quick exit from the interrupt if no active video line is to be drawn during the current vertical line. The sound system is capable of simple sound effects and music by setting the value of R2 anytime in the main loop. Low values will create low frequencies and high values, higher frequencies. The sound output is just a simple piezo buzzer plugged directly into PORT B.7. You could also add a 100K resistor and feed it into an amplifier or line input. Sound is very basic though, only as good as the old IBM PC!

That is basically the entire video rendering interrupt, besides "HORIZONTAL FRONT PORCH = 12 CYCLES", which just restores the status register and ends the interrupt after the last pixel has been drawn. Because of the way the video driver controls the bus and offers the MemReady flag on R25, your main loop is free to draw to the hidden video buffer at its leisure and then issue a command to swap buffers to move onto the next frame. Several additional subroutines have been added to do the page flipping, page clearing, as well as draw some text and sprites to the screen.

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